1. Technical Field
The invention relates to a semiconductor memory device and, more particularly, to a multi-path accessible semiconductor memory device that is suitable for a portable communication system.
2. Discussion of Related Art
In general, a semiconductor memory device having a plurality of access ports is called a multi-port memory device. Particularly, a memory device having two access ports is called a dual-port memory. A typical and well known dual-port memory is an image processing video memory having a random access memory (RAM) port enabling accessing in a random sequence and a serial access memory (SAM) port enabling accessing only in a serial sequence.
On the other hand, a dynamic random access memory (DRAM) in which a shared memory area in a memory cell array including DRAM cells with no SAM port may be read or written through a plurality of access ports. Hereinafter, DRAM is referred to as a multi-path accessible semiconductor memory device so that it is distinguished from a multi-port memory such as the video memory.
For modern portable electronic systems such as handheld phones or personal digital assistants (PDAs), manufacturers have developed multi-processor systems equipped with a plurality of processors to perform functions faster and to allow smoother operations, as shown in FIG. 1.
Referring to FIG. 1, a first processor 10 and a second processor 12 are connected with each other via a connection line L10; a NOR memory 14 and a DRAM 16 are connected to the first processor 10 via buses B1 to B3; and a DRAM 18 and a NAND memory 20 are connected to the second processor 12 via buses B4 to B6. The first processor 10 may have a MODEM function of modulating and demodulating a communication signal, and the second processor 12 may have an application function of processing communication data or performing games, moving images, and the like. The NOR memory 14 having a cell array of a NOR structure and the NAND memory 20 having a cell array of a NAND structure are both non-volatile memories each including transistor memory cells with a floating gate. The NOR memory 14 and the NAND memory 20 store data, e.g., a unique code and preserved data of a portable device, which should be not erased even when power is off. DRAMS 16 and 18 function as main memories for data processing at the processors 10, 12.
In the multi-processor system as shown in FIG. 1, the DRAMs are allocated to each corresponding processor, and relatively low speed UART, SPI and SRAM interfaces are used. Accordingly, it is difficult to obtain a sufficient data transmission rate. In addition, the structure is complex and cost increases. A scheme for reducing occupancy size, increasing data transmission rate, and reducing the number of memories is shown in FIG. 2.
Referring to FIG. 2, one DRAM 17 is connected to first and second processors 10 and 12 through buses B1 and B2, unlike the system of FIG. 1. In the multi-processor system of FIG. 2, two ports need to be connected to the corresponding buses B1 and B2 in order to enable the respective processors to access the DRAM 17 through the two paths.
A typical DRAM is a memory 1 having a single input/output path 16 and a single port PO, as shown in FIG. 3, The typical DRAM structure comprises a memory cell array that may include first to fourth banks 3, 4, 5 and 6, each having a row decoder 8 and a column decoder 7. An upper input/output sense amplifier and driver 13 is operably connected to the first bank 3 or the third bank 5 via a multiplexer 11 or 12, and a lower input/output sense amplifier and driver 15 is operably connected to the second bank 4 or the fourth bank 6 via a multiplexer 19 or 14. In this typical DRAM structure, a process of outputting the read data from two memory banks is as follows. For example, when data stored in a selected memory cell in the first bank 3 is read, the selected word line is activated. Data in the memory cell sensed and amplified by a bit line sense amplifier in the array is transferred to a local input/output line pair (LIO) 9 through an activated column select line CSL. The data transferred to the local input/output line pair (LIO) 9 is transferred to a global input/output line pair (GIO) 10 by switching operation of a first multiplexer 21. The second multiplexer 11 connected to the global input/output line pair (GIO) 10 transfers the data on the global input/output line pair 10 to the upper input/output sense amplifier and driver 13. The data sensed and amplified by the input/output sense amplifier and driver 13 is then output to the data output line L5 through a path 16. Meanwhile, when data stored in a memory cell in the fourth bank 6 is read, the data is output to an output terminal DQ via a multiplexer 24—the multiplexer 14—the lower input/output sense amplifier and driver 15—the path 16—the data output line L5. As seen above, DRAM 1 of FIG. 3 is a single port memory in which the two banks share one input/output sense amplifier and driver and data input/output is performed through one port PO. As a result, DRAM 1 of FIG. 3 may be applied only to the system of FIG. 1 and is difficult to apply to the multi-processor system of FIG. 2 due to the structures of the memory banks and the port.
In order to implement a memory suitable for the multi-processor system as shown in FIG. 2, a shared memory area can be accessed by a plurality of processors as shown in FIG. 4 and disclosed in U.S. Publication No. 2003/0093628 published on May 15, 2003.
Referring to FIG. 4, a multi-processor system 50 is shown in which a memory array 35 includes first, second and third portions. In the memory array 35, the first portion 33 is accessed only by a first processor 70 through a port 37, the second portion 31 is accessed only by a second processor 80 through a port 38, and the third portion 32 is accessed by both the first and second processors 70 and 80. Here, sizes of the first and second portions 33 and 31 in the memory array 35 may be changed depending on a load of the first and second processors 70 and 80, and the memory array 35 is of a memory type or a disc storage type.
To implement the memory array 35 using a DRAM structure and allow the first and second processors 70 and 80 to share the third portion 32, some problems need to be overcome. For example, there is a need for a technique for effectively laying out memory areas and input/output sense amplifiers in the memory array 35 and for controlling a read/write path for each port. There is also a need for a technique for enabling external processors corresponding to respective ports to recognize a current use state of a shared memory area (e.g., an occupancy state or a busy state).
Accordingly, there is a need for a solution for sharing a memory area of a DRAM memory cell array in a multi-processor system having two or more processors and an enhanced method for notifying one processor of port occupancy state information indicating whether the shared memory area in the memory cell array is accessed by another processor.